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1/12 december 2002 n 100ps part-to part skew n 50ps bank skew n differential design n meets lvds spec. for driver outputs and receiver inputs n reference voltage available output v bb n low voltage v cc range of 2.375v to 2.625v n high signalling rate capability (exceeds 622mhz) n support open, short and terminated input fail-safe (low output state) n programmable drivers power off control description the STLVD111 is a low skew programmable 1 to 10 differential lvds driver, designed for clock distribution. the select signal is fanned out to 10 identical differential outputs. the STLVD111 is provided with a 11 bit shift register with a serial in and a control register. the purpose is to enable or power off each output clock channel and to select the clock input. the STLVD111 is specifically designed, modelled and produced with low skew as the key goal. optimal design and layout serve to minimize gate to gate skew within a device. the net result is a dependable guaranteed low skew device. the STLVD111 can be used for high performance clock distribution in 2.5v systems with lvds levels. designers can take advantage of the devices performance to distribute low skew clocks across the backplane or the board. ordering codes ty pe temperature range package comments STLVD111bf -40 to 85 c tqfp32 (tray) 250 parts per tray STLVD111bfr -40 to 85 c tqfp32 (tape & reel) 2400 parts per reel STLVD111 programmable low voltage 1:10 differential lvds clock driver tqfp32
STLVD111 2/12 pin configuration pin description pln n symbol name and function 1 ck control register clock 2 si control register serial in/clk_sel 3 clk0 differential input 4 clk0 differential input 5 v bb output reference voltage 6 clk1 differential input 7 clk1 differential input 8 en device enable/program 9 gnd ground 10 q9 differential outputs 11 q9 differential outputs 12 q8 differential outputs 13 q8 differential outputs 14 q7 differential outputs 15 q7 differential outputs 16 v cc supply voltage 17 q6 differential outputs 18 q6 differential outputs 19 q5 differential outputs 20 q5 differential outputs 21 q4 differential outputs 22 q4 differential outputs 23 q3 differential outputs 24 q3 differential outputs 25 gnd ground 26 q2 differential outputs 27 q2 differential outputs 28 q1 differential outputs 29 q1 differential outputs 30 q0 differential outputs 31 q0 differential outputs 32 v cc supply voltage
STLVD111 3/12 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. thermal data recommended operating conditions driver electrical characteristics (t a = -40 to 85 c, v cc = 2.5v 5%, unless otherwise specified (note 1, 2) note 1: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise specified. note 2: all typical values are given for v cc =2.5vandt a = 25c unless otherwise stated. receiver electrical characteristics (t a =-40to85c,v cc = 2.5v 5%, unless otherwise specified (note 1, 2) note 1: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise specified. note 2: all typical values are given for v cc =2.5vandt a = 25c unless otherwise stated. symbol parameter value unit v cc supply voltage -0.3 to 2.8 v v i input voltage -0.2 to (v cc +0.2) v v o output voltage -0.2 to (v cc +0.2) v i osd driver short circuit current continuous esd electrostatic discharge (hbm 1.5k w, 100pf) >2 kv symbol parameter value unit r tj-c thermal resistance junction-case 13 c/w symbol parameter min typ max unit v cc supply voltage 2.375 2.625 v v ic receiver common mode input voltage 0.5(v id ) 2-0.5(v id ) v t a operating free-air temperature range -40 85 c t j operating junction temperature -40 105 c symbol parameter test conditions value unit min. typ. max. v od output differential voltage (fig. 2) r l =100 w 400 500 600 mv d v od v od magnitude change 30 mv v os offset voltage -40 t a 85c 1.05 1.15 1.25 v d v os v os magnitude change 30 v i os output short circuit current v o =0v 15 30 ma v od =0v 7 15 symbol parameter test conditions value unit min. typ. max. v idh input threshold high 100 mv v idl input threshold low -100 mv i in input current v i = 0v 42 100 m a v i =0v cc 210
STLVD111 4/12 driver electrical characteristics (t a = -40 to 85 c, v cc = 2.5v 5%, unless otherwise specified (note 1, 2) note 1: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise specified. note 2: all typical values are given for v cc =2.5vandt a = 25c unless otherwise stated. lvds timing characteristics (t a = -40 to 85 c, v cc = 2.5v 5%, unless otherwise specified (note 4) note 4: generator waveforms for all test conditions: f=1mhz, z o =50 w (unless otherwise specified). control register timing characteristics (t a =-40to85c,v cc = 2.5v 5%, en=h, unless otherwise specified (figure 4) symbol parameter test conditions value unit min. typ. max. v bb output reference voltage v cc = 2.5 v 1.15 1.25 1.35 v i ccd power supply current all driver enabled and loaded 125 160 ma c in input capacitance v i =0vtov cc 5pf c out output capacitance 5 pf v ih logic input high threshold v cc = 2.5 v 2 v v il logic input low threshold v cc = 2.5 v 0.8 v i i logic input current v cc = 2.5 v, v in =v cc or gnd 10 a symbol parameter test conditions value unit min. typ. max. t tlh, t thl transition time r l = 100 w ,c l = 5 pf, fig. 5, 6) 220 300 ps t phl, t plh propagation delay time (fig. 5, 6) 2 2.5 ns f max maximum input frequency 700 900 mhz t skew bank skew (fig. 1) 50 ps part to part skew (fig. 2) 100 pulse skew (fig. 3) 50 symbol parameter test conditions value unit min. typ. max. f max maximum frequency of shift register (fig. 7) 100 150 mhz t s clock to si setup time (fig. 7) 2 ns t h clock to si hold time (fig. 7) 1.5 ns t rem enable to clock removal time (fig. 7) 1.5 ns t w minimum clock pulse width (fig. 7) 3 ns
STLVD111 5/12 specification of control register the STLVD111 is provided with a 11 bit shift register with a serial in and a control register. the purpose is to enable or power of each output clock channel and to select the clock input. the STLVD111 provides two working modality: programmed mode (en=1) the shift register have a serial input to load the working configuration. once the configuration is loaded with 11 clock pulse, another clock pulse load the configuration into the control register. the first bit on the serial input line enables the outputs q9 and q9 , the second bit enables the outputs q8 and q8 and so on. the last bit is the clock selection bit. to restart the configuration of the shift register a reset of the state machine must be done with a clock pulse on ck and the en set to low. the control register shift register can be configured on time after each reset. standard mode (en=0) in standard mode the STLVD111 isnt programmable, all the clock outputs are enabled. the lvds clock input is selected from clock 0 or clock 1 with the si pin as shown in the truth table below. truth table of state machine inputs serial input sequence truth table of the control register truth table en si ck output l l x all output enabled, clock 0 selected, control register disabled l h x all output enabled, clock 1 selected, control register disabled hl first stage stores "l", other stages store the data of previous stage hh first stage stores "h", other stages store the data of previous stage lx reset of the state machine, shift register and control register bit#10 bit#9 bit#8 bit#7 bit#6 bit#5 bit#4 bit#3 bit#2 bit#1 bit#0 clk_sel q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 bit#10 bit#(0-9) qn(0-9) l h clock 0 h h clock 1 x l qn output disabled ck en si clk 0 clk 0 clk 1 clk 1 q (0-9) q (0-9) llllhxxlh lllhlxxhl l l l open open x x l h llhxxlhlh l lhxxhlhl l l h x x open open l h all drivers enable
STLVD111 6/12 logic diagram
STLVD111 7/12 figure 1 : bank skew - t sk(b) figure 2 : part to part skew - t sk(pp) figure 3 : pulse skew - t sk(p) t sk(b) : bankskew is the magnitude of the time difference between outputs with a single driving input terminal t sk(pp) : part to part skew is the magnitude of the difference in propagation delay times between any specific terminals of two devices when both devices operate with the same input signals, the same supply voltages, and the same temperature, and have identical packages and test circuits. tsk(b): pulse skew is the magnitude of the time difference between the high to low and low to high propagation delay times at an output.
STLVD111 8/12 figure 4 : voltage and current definition figure 5 : test circuit and voltage definition for the differential output signal
STLVD111 9/12 figure 6 : differential receiver to drive propagation delay and drive transition time waveforms figure 7 : set-up, hold and the removal time, maximum frequency, minimum pulse width waveforms
STLVD111 10/12 dim. mm. inch min. typ max. min. typ. max. a 1.6 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.0035 0.0079 d 9.00 0.354 d1 7.00 0.276 d3 5.60 0.220 e 0.80 0.031 e 9.00 0.354 e1 7.00 0.276 e3 5.60 0.220 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?3.5?7? 0?3.5?7? tqfp32 mechanical data 0060661/c a a2 a1 b seating plane c 8 9 16 17 24 25 32 e3 d3 e1 e d1 d e 1 k b tqfp32 l l1 0.10mm .004
STLVD111 11/12 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 9.5 9.7 0.374 0.382 bo 9.5 9.7 0.374 0.382 ko 2.1 2.3 0.083 0.091 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tqfp32 mechanical data
STLVD111 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

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